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rev.0.80 mar 18, 2005 page 1 of 34 rej03b0088-0080 preliminary m16c/30p group single-chip 16-bit cmos microcomputer notice: this is not a final specification. some parametric limits are subject to change. rej03b0088-0080 rev.0.80 mar 18, 2005 1. overview the m16c/30p group of single-chip microcomputers are built using the high-performance silicon gate cmos process using a m16c/60 series cpu co re and are packaged in a 1 00-pin plastic molded qfp. these single-chip microco mputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, they are capabl e of executing instructions at high speed. in addition, this microcomputer contains a multiplier and dmac which combined with fast instruction processing capability, makes it suitable for control of various oa, communication, and indu strial equipment which requir es high-speed arithmetic/ logic operations. 1.1 applications audio, cameras, tv, home applia nce, office/communications/porta ble/industrial equipment, etc. specifications written in this ma nual are believed to be accurate, but are not guarante ed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition.
under development m16c/30p group 1. overview preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 2 of 34 rej03b0088-0080 1.2 performance outline table 1.1 lists performance outline of m16c/30p group. notes: 1. i 2 c bus is a registered trademark of koninklijke philips electronics n. v. 2. iebus is a registered trademark of nec electronics corporation. 3. use the m16c/30p on vcc1 = vcc2. table 1.1 performance outline of m16c/30p group item performance cpu number of basic inst ructions 91 instructions minimum instruction execution time 62.5ns(f(xin)=16mhz, vcc1=vcc2=4.2 to 5.5v, no wait) 100ns(f(xin)=10mhz, vcc1=v cc2=2.7 to 5.5v, no wait) operation mode single-chip memory space 1 mbyte memory capacity see table 1.2 product list peripheral function port input/output : 87 pins, input : 1 pin multifunction timer timer a : 16 bits x 3 channels, timer b : 16 bits x 3 channels serial interface 3 channels clock synchronous, uart, i 2 c bus (1) 1 channels iebus (2) a/d converter 10-bit a/d conver ter: 1 circuit, 18 channels dmac 2 channels crc calculation circuit ccitt-crc watchdog timer 15 bits x 1 channel (with prescaler) interrupt internal: 20 sources, external: 7 sources, software: 4 sources, priority level: 7 levels clock generating circuit 2 circuits main clock generation circuit (*), subclock generation circuit (*), (*)equipped with a built-in feedback resistor. electric characteristics supply voltage vcc1=vcc2=3.0 to 5.5 v (f(xin)=16mhz) vcc1=vcc2=2.7 to 5.5 v (f(xin)=10mhz, no wait) power consumption 10 ma (v cc1=vcc2=5v, f(xin)=16mhz) 8 ma (vcc1=vcc2=3v, f(xin)=10mhz) 1.8 a (vcc1=vcc2=3v, f(xcin)=32khz, wait mode) 0.7 a(vcc1=vcc2=3v, stop mode) operating ambient temperature -20 to 85 c, -40 to 85 c package 100-pin plastic mold qfp, lqfp
under development m16c/30p group 1. overview preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 3 of 34 rej03b0088-0080 1.3 block diagram figure 1.1 is a m16c/30p group block diagram. figure 1.1 m16c/30p group block diagram output (timer a): 3 input (timer b): 3 internal peripheral functions watchdog timer (15 bits) dmac (2 channels) memory rom (1) ram (2) a/d converter (10 bits x 18 channels ) uart or clock synchronous serial i/o (3 channels) system clock generation circuit xin-xout xcin-xcout m16c/60 series16-bit cpu core port p0 8 port p1 8 port p2 8 8 8 8 port p6 8 8 r0l r0h r1h r1l r2 r3 a0 a1 fb sb isp usp intb crc arithmetic circuit (ccitt ) (polynomial : x 16 +x 12 +x 5 +1) multiplier 7 8 8 port p10 port p9 port p8_5 port p8 port p7 notes : 1. rom size depends on microcomputer type. 2. ram size depends on microcomputer type. port p5 port p4 port p3 pc flg timer (16-bit)
under development m16c/30p group 1. overview preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 4 of 34 rej03b0088-0080 1.4 product list table 1.2 lists the m16c/30p group products and figur e 1.2 shows the type no., memory size, and package. (d): under development (p): under planning figure 1.2 type no., memory size, and package table 1.2 product list as of mar 2005 type no. rom capacity ram ca pacity package type remarks M30302MAP-XXXFP (d) 96 kbytes 5 kbytes 100p6s-a mask rom version m30302map-xxxgp (d) 100p6q-a m30302mcp-xxxfp (d) 128 kbytes 100p6s-a m30302mcp-xxxg p (d) 100p6q-a m30302mep-xxxfp (d) 192 kbytes 6 kbytes 100p6s-a m30302mep-xxxgp (d) 100p6q-a package type: fp : package 100p6s-a gp : package 100p6q-a rom no. memory type: m : mask rom version type no. m 3 0 3 0 2 m e p - x x x f p shows ram capacity, pin count, etc (the value itself has no specific meaning) m16c/30 series m16c family rom capacity: a : 96 kbytes c : 128 kbytes e : 192 kbytes m16c/30p group
under development m16c/30p group 1. overview preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 5 of 34 rej03b0088-0080 1.5 pin configuration figures 1.3 to 1.4 show the pin configurations (top view). figure 1.3 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0_0/an0_0 p0_1/an0_1 p0_2/an0_2 p0_3/an0_3 p0_4/an0_4 p0_5/an0_5 p0_6/an0_6 p0_7/an0_7 p1_0 p1_1 p1_2 p1_3 p1_4 vref avss vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p3_0 p3_1 p3_2 p3_3 p3_4 p3_5 p3_6 p3_7 p4_0 p4_1 p4_2 p4_3 p7_4/ta2out p7_6 p5_6 p7_7 p5_5 p5_4 p5_3 p5_2 vcc2 vss p5_7/clkout p4_5 p4_6 p4_7 avcc p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_3 p9_4 p9_5/anex0 p9_6/anex1 p9_1/tb1in p9_2/tb2in p8_0 p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p7_2/clk2/ta1out p8_2/int0 p7_1/rxd2/scl2/ta0in (1) p8_3/int1 p8_5/nmi p9_7/adtrg p4_4 p5_0 p5_1 p9_0/tb0in p7_0/txd2/sda2/ta0out (1) p8_4/int2 p8_1 p7_3/cts2/rts2/ta1in p7_5/ta2in p1_5/int3 p1_6/int4 p1_7 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 p2_0 p2_1 p2_2 p2_3 p2_4 p2_5 p2_6 p2_7 m16c/30p group package : 100p6s-a pin configuration (top view) notes: 1. p7_0 and p7_1 are n channel open-drain output pins. 2. use the m16c/30p on vcc1=vcc2.
under development m16c/30p group 1. overview preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 6 of 34 rej03b0088-0080 figure 1.4 pin configuration (top view) 12345678910111213141516171819202122232425 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0_0/an0_0 p0_1/an0_1 p0_2/an0_2 p0_3/an0_3 p0_4/an0_4 p0_5/an0_5 p0_6/an0_6 p0_7/an0_7 p1_0 p1_1 p1_2 p1_3 p1_4 vref avss p2_0 p2_1 p2_2 p2_3 p2_4 p2_5 p2_6 p2_7 p3_0 p3_1 p3_2 p3_3 p3_4 p3_5 p3_6 p3_7 p4_0 p4_1 p4_2 p4_3 vcc2 vss avcc p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_5/anex0 p9_6/anex1 p9_7/adtrg p7_2/clk2/ta1out p7_1/rxd2/scl2/ta0in (1) p7_0/txd2/sda2/ta0out (1) p1_5/int3 p1_6/int4 p1_7 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p7_4/ta2out p7_6 p7_7 p9_3 p9_4 p9_1/tb1in p9_2/tb2in p8_0 p8_2/int0 p8_3/int1 p8_5/nmi p9_0/tb0in p8_4/int2 p8_1 p7_3/cts2/rts2/ta1in p7_5/ta2in p5_6 p5_5 p5_4 p5_3 p5_2 p5_7/clkout p4_5 p4_6 p4_7 p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p4_4 p5_0 p5_1 m16c/30p group pin configuration (top view) package : 100p6q-a notes: 1. p7_0 and p7_1 are n channel open-drain output pins. 2. use the m16c/30p on vcc1=vcc2.
under development m16c/30p group 1. overview preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 7 of 34 rej03b0088-0080 1.6 pin description i : input o : output i/o : input and output table 1.3 pin description (1) signal name pin name i/o type description power supply input vcc1, vcc2 vss i apply 2.7 to 5.5 v to the vcc1 and vcc2 pins and 0 v to the v ss pin. the vcc apply condition is that vcc1 = vcc2. analog power supply input avcc avss i applies the power supply for the a/d converter. connect the avcc pin to vcc1. connect the avss pin to vss. reset input reset i the microcomputer is in a reset state when applying ?l? to the this pin. cnvss cnvss i connect this pin to vss. external data bus width select input byte i main clock input xin i i/o pins for the main clock generation circuit. connect a ceramic resonator or crystal oscillator between xin and xout. to use the external clock, input the clock from xin and leave xout open. main clock output xout o sub clock input xcin i i/o pins for a sub clo ck oscillation circuit. connect a crystal oscillator between xcin and xcout. to use the external clock, input the clock from xcin and leave xcout open. sub clock output xcout o clock output clkout o the clock of the same cycle as fc, f8, or f32 is outputted. int interrupt input int0 to int4 i input pins for the int interrupt. nmi interrupt input nmi i input pin for the nmi interrupt. key input interrupt input ki0 to ki3 i input pins for the key input interrupt. timer a ta0out to ta2out i/o these are timer a0 to timer a2 i/o pins. (except the output of ta0out for the n-channel open drain output.) ta0in to ta2in i these are timer a0 to timer a2 input pins. timer b tb0in to tb2in i these are timer b0 to timer b2 input pins. serial interface cts0 to cts2 i these are send control input pins. rts0 to rts2 o these are receive control output pins. clk0 to clk2 i/o these are transfer clock i/o pins. rxd0 to rxd2 i these are serial data input pins. txd0 to txd2 o these are serial data output pins. (except txd2 for the n-channel open drain output.) clks1 o this is output pin for transfer clock output from multiple pins function. i 2 c mode sda0 to sda2 i/o these are serial data i/o pins. (except sda2 for the n-channel open drain output.) scl0 to scl2 i/o these are transfer clock i/o pins. (except scl2 for the n-channel open drain output.)
under development m16c/30p group 1. overview preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 8 of 34 rej03b0088-0080 i : input o : output i/o : input and output table 1.4 pin description (2) signal name pin name i/o type description reference voltage input vref i applies the reference voltage for the a/d converter. a/d converter an0 to an7, an0_0 to an0_7 i analog input pins for the a/d converter. adtrg i this is an a/d trigger input pin. anex0 i/o this is the extended analog input pin for the a/d converter, and is the output in external op-amp connection mode. anex1 i this is the extended analog input pin for the a/d converter. i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p9_0 to p9_7, p10_0 to p10_7 i/o 8-bit i/o ports in cmos, having a direction register to select an input or output. each pin is set as an input port or output port. an input port can be set for a pull-up or for no pull-up in 4-bi t unit by program. (except p7_0 and p7_1 for the n-channel open drain output.) p8_0 to p8_4, p8_6, p8_7 i/o i/o ports having equivalent functions to p0. input port p8_5 i input pin for the nmi interrupt. pin states can be read by the p8_5 bit in the p8 register.
under development m16c/30p group 2. central processing unit (cpu) preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 9 of 34 rej03b0088-0080 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. figure 2.1 central processing unit register 2.1 data registers (r 0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32-bit data register (r2r0). r3r1 is the same as r2r0. data registers (1) address registers (1) frame base registers (1) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register notes: 1. these registers comprise a register bank. there are two register banks. r0h b15 b8 b7 b0 r3 intbh usp isp sb c d z s b o i u ipl r0l r1h r1l r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt en able flag stack pointer select flag reserved area processor interrupt priority level
under development m16c/30p group 2. central processing unit (cpu) preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 10 of 34 rej03b0088-0080 2.2 address registers (a0 and a1) the register a0 consists of 16 bits, an d is used for address regist er indirect addressing an d address register relative addressing. they also are used for transfers and logic/logic opera tions. a1 is the same as a0. in some instructions, registers a1 and a0 can be co mbined for use as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating th e start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured wi th 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out b it that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to ?0?. 2.8.3 zero flag (z flag) this flag is set to ?1? when an arithmetic operation resulted in 0; otherwise, it is ?0?. 2.8.4 sign flag (s flag) this flag is set to ?1? when an arithmetic operation resulted in a nega tive value; otherwise, it is ?0?. 2.8.5 register bank se lect flag (b flag) register bank 0 is selected when this flag is ?0? ; register bank 1 is selected when this flag is ?1?. 2.8.6 overflow flag (o flag) this flag is set to ?1? when the operation resulted in an overflow; otherwise, it is ?0?. 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabl ed when the i flag is ?0?, and are enab led when the i flag is ?1?. the i flag is cleared to ?0? when the interrupt request is accepted.
under development m16c/30p group 2. central processing unit (cpu) preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 11 of 34 rej03b0088-0080 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is ?0?; usp is selected when the u flag is ?1?. the u flag is cleared to ?0? when a hardware interrupt request is accepte d or an int instru ction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor in terrupt priority le vels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. 2.8.10 reserved area when write to this bit, write ?0?. when read, its content is indeterminate.
under development m16c/30p group 3. memory preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 12 of 34 rej03b0088-0080 3. memory figure 3.1 is a memory map of the m16c/30p group . the address space extends the 1m bytes from address 00000h to fffffh. the internal rom is allocated in a lower address directio n beginning with address ffff fh. for example, a 64-kbyte internal rom is allocated to the addresses from f0000h to fffffh. the fixed interrupt vector table is al located to the addresses from fffdch to fffffh. therefore, store the start address of each inte rrupt routine here. the internal ram is allocated in an upper address direction beginning with address 00400h. for example, a 10-kbyte internal ram is allocated to the addresses from 00400h to 02bffh. in addition to storing data, the internal ram also stores the stack used when cal ling subroutines and when inte rrupts are generated. the sfr is allocated to the addresses from 00000h to 003ffh. peripheral function control regi sters are located here. of the sfr, any area which has no functions allocated is reserved for future use and cannot be used by users. the special page vector table is allocat ed to the addresses from ffe00h to ff fdbh. this vector is used by the jmps or jsrs instruction. for details, refer to the m16c/60 and m16c/20 s eries software manual . figure 3.1 memory map internal rom reset watchdog timer single step address match brk instruction overflow undefined instruction special page vector table yyyyyh fffffh fffffh fffdch ffe00h dbc nmi size address yyyyyh 128 kbytes e0000h size address xxxxxh internal ram internal rom 5 kbytes 017ffh 6 kbytes 01bffh 96 kbytes e8000h 192 kbytes d0000h sfr internal ram reserved area 00000h 00400h xxxxxh
under development m16c/30p group 4. special function register (sfr) preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 13 of 34 rej03b0088-0080 4. special function register (sfr) sfr(special function register) is the c ontrol register of peripheral functions. tables 4.1 to 4.5 list the sfr information. notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. the pm00 and pm01 bits do not change at software reset. x : nothing is mapped to this bit table 4.1 sfr information(1) (1) address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 (2) pm0 00h 0005h processor mode register 1 pm1 00xxx0xxb 0006h system clock control register 0 cm0 01001000b 0007h system clock control register 1 cm1 00100000b 0008h 0009h address match interrupt enable register aier xxxxxx00b 000ah protect register prcr xx000000b 000bh 000ch 000dh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00xxxxxxb 0010h address match interrupt register 0 rmad0 00h 0011h 00h 0012h x0h 0013h 0014h address match interrupt register 1 rmad1 00h 0015h 00h 0016h x0h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh 0020h dma0 source pointer sar0 xxh 0021h xxh 0022h xxh 0023h 0024h dma0 destination pointer dar0 xxh 0025h xxh 0026h xxh 0027h 0028h dma0 transfer counter tcr0 xxh 0029h xxh 002ah 002bh 002ch dma0 control register dm0con 00000x00b 002dh 002eh 002fh 0030h dma1 source pointer sar1 xxh 0031h xxh 0032h xxh 0033h 0034h dma1 destination pointer dar1 xxh 0035h xxh 0036h xxh 0037h 0038h dma1 transfer counter tcr1 xxh 0039h xxh 003ah 003bh 003ch dma1 control register dm1con 00000x00b 003dh 003eh 003fh
under development m16c/30p group 4. special function register (sfr) preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 14 of 34 rej03b0088-0080 notes: 1. the blank areas are reserved an d cannot be accessed by users. x : nothing is mapped to this bit table 4.2 sfr information(2) (1) address register symbol after reset 0040h 0041h 0042h 0043h 0044h int3 interrupt control register int3ic xx00x000b 0045h 0046h uart1 bus collision detection interrupt control register u1bcnic xxxxx000b 0047h uart0 bus collision detection interrupt control register u0bcnic xxxxx000b 0048h 0049h int4 interrupt control register int4ic xx00x000b 004ah uart2 bus collision detection interrupt control register bcnic xxxxx000b 004bh dma0 interrupt control register dm0ic xxxxx000b 004ch dma1 interrupt control register dm1ic xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh uart2 transmit interrupt control register s2tic xxxxx000b 0050h uart2 receive interrupt control register s2ric xxxxx000b 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h timer a0 interrupt control register ta0ic xxxxx000b 0056h timer a1 interrupt control register ta1ic xxxxx000b 0057h timer a2 interrupt control register ta2ic xxxxx000b 0058h 0059h 005ah timer b0 interrupt control register tb0ic xxxxx000b 005bh timer b1 interrupt control register tb1ic xxxxx000b 005ch timer b2 interrupt control register tb2ic xxxxx000b 005dh int0 interrupt control register int0ic xx00x000b 005eh int1 interrupt control register int1ic xx00x000b 005fh int2 interrupt control register int2ic xx00x000b 0060h to 024fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025ah 025bh 025ch 025dh 025eh peripheral clock select register pclkr 00000011b 025fh 0260h to 0335h 0336h 0337h 0338h 0339h 033ah 033bh 033ch 033dh 033eh 033fh
under development m16c/30p group 4. special function register (sfr) preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 15 of 34 rej03b0088-0080 notes: 1. the blank areas are reserved an d cannot be accessed by users. x : nothing is mapped to this bit table 4.3 sfr information(3) (1) address register symbol after reset 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034ah 034bh 034ch 034dh 034eh 034fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035ah 035bh 035ch 035dh 035eh interrupt factor select register 2 ifsr2a 00xxxxxxb 035fh interrupt factor select register ifsr 00h 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036ah 036bh 036ch uart0 special mode register 4 u0smr4 00h 036dh uart0 special mode register 3 u0smr3 000x0x0xb 036eh uart0 special mode register 2 u0smr2 x0000000b 036fh uart0 special mode register u0smr x0000000b 0370h uart1 special mode register 4 u1smr4 00h 0371h uart1 special mode register 3 u1smr3 000x0x0xb 0372h uart1 special mode register 2 u1smr2 x0000000b 0373h uart1 special mode register u1smr x0000000b 0374h uart2 special mode register 4 u2smr4 00h 0375h uart2 special mode register 3 u2smr3 000x0x0xb 0376h uart2 special mode register 2 u2smr2 x0000000b 0377h uart2 special mode register u2smr x0000000b 0378h uart2 transmit/receive mode register u2mr 00h 0379h uart2 bit rate generator u2brg xxh 037ah uart2 transmit buffer register u2tb xxh 037bh xxh 037ch uart2 transmit/receive control register 0 u2c0 00001000b 037dh uart2 transmit/receive control register 1 u2c1 00000010b 037eh uart2 receive buffer register u2rb xxh 037fh xxh
under development m16c/30p group 4. special function register (sfr) preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 16 of 34 rej03b0088-0080 notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. bit 5 in the up-down flag is ?0? by reset. however, the values in these bits when read are indeterminate. x : nothing is mapped to this bit table 4.4 sfr information(4) (1) address register symbol after reset 0380h count start flag tabsr 000xx000b 0381h clock prescaler reset fag cpsrf 0xxxxxxxb 0382h one-shot start flag onsf 00xxx000b 0383h trigger select register trgsr xxxx0000b 0384h up-down flag udf xx0xx000b (2) 0385h 0386h timer a0 register ta0 xxh 0387h xxh 0388h timer a1 register ta1 xxh 0389h xxh 038ah timer a2 register ta2 xxh 038bh xxh 038ch 038dh 038eh 038fh 0390h timer b0 register tb0 xxh 0391h xxh 0392h timer b1 register tb1 xxh 0393h xxh 0394h timer b2 register tb2 xxh 0395h xxh 0396h timer a0 mode register ta0mr 00h 0397h timer a1 mode register ta1mr 00h 0398h timer a2 mode register ta2mr 00h 0399h 039ah 039bh timer b0 mode register tb0mr 00xx0000b 039ch timer b1 mode register tb1mr 00xx0000b 039dh timer b2 mode register tb2mr 00xx0000b 039eh 039fh 03a0h uart0 transmit/receive mode register u0mr 00h 03a1h uart0 bit rate generator u0brg xxh 03a2h uart0 transmit buffer register u0tb xxh 03a3h xxh 03a4h uart0 transmit/receive control register 0 u0c0 00001000b 03a5h uart0 transmit/receive control register 1 u0c1 00000010b 03a6h uart0 receive buffer register u0rb xxh 03a7h xxh 03a8h uart1 transmit/receive mode register u1mr 00h 03a9h uart1 bit rate generator u1brg xxh 03aah uart1 transmit buffer register u1tb xxh 03abh xxh 03ach uart1 transmit/receive control register 0 u1c0 00001000b 03adh uart1 transmit/receive control register 1 u1c1 00000010b 03aeh uart1 receive buffer register u1rb xxh 03afh xxh 03b0h uart transmit/receive control register 2 ucon x0000000b 03b1h 03b2h 03b3h 03b4h 03b5h 03b6h 03b7h 03b8h dma0 request factor select register dm0sl 00h 03b9h 03bah dma1 request factor select register dm1sl 00h 03bbh 03bch crc data register crcd xxh 03bdh xxh 03beh crc input register crcin xxh 03bfh
under development m16c/30p group 4. special function register (sfr) preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 17 of 34 rej03b0088-0080 notes: 1. the blank areas are reserved an d cannot be accessed by users. x : nothing is mapped to this bit table 4.5 sfr information(5) (1) address register symbol after reset 03c0h a/d register 0 ad0 xxh 03c1h xxh 03c2h a/d register 1 ad1 xxh 03c3h xxh 03c4h a/d register 2 ad2 xxh 03c5h xxh 03c6h a/d register 3 ad3 xxh 03c7h xxh 03c8h a/d register 4 ad4 xxh 03c9h xxh 03cah a/d register 5 ad5 xxh 03cbh xxh 03cch a/d register 6 ad6 xxh 03cdh xxh 03ceh a/d register 7 ad7 xxh 03cfh xxh 03d0h 03d1h 03d2h 03d3h 03d4h a/d control register 2 adcon2 xxx000x0b 03d5h 03d6h a/d control register 0 adcon0 000x0xxxb 03d7h a/d control register 1 adcon1 00000xxxb 03d8h 03d9h 03dah 03dbh 03dch 03ddh 03deh 03dfh 03e0h port p0 register p0 xxh 03e1h port p1 register p1 xxh 03e2h port p0 direction register pd0 00h 03e3h port p1 direction register pd1 00h 03e4h port p2 register p2 xxh 03e5h port p3 register p3 xxh 03e6h port p2 direction register pd2 00h 03e7h port p3 direction register pd3 00h 03e8h port p4 register p4 xxh 03e9h port p5 register p5 xxh 03eah port p4 direction register pd4 00h 03ebh port p5 direction register pd5 00h 03ech port p6 register p6 xxh 03edh port p7 register p7 xxh 03eeh port p6 direction register pd6 00h 03efh port p7 direction register pd7 00h 03f0h port p8 register p8 xxh 03f1h port p9 register p9 xxh 03f2h port p8 direction register pd8 00x00000b 03f3h port p9 direction register pd9 00h 03f4h port p10 register p10 xxh 03f5h 03f6h port p10 direction register pd10 00h 03f7h 03f8h 03f9h 03fah 03fbh 03fch pull-up control register 0 pur0 00h 03fdh pull-up control register 1 pur1 00h 03feh pull-up control register 2 pur2 00h 03ffh port control register pcr 00h
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 18 of 34 rej03b0088-0080 5. electrical characteristics table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc supply voltage(v cc1 =v cc2 )v cc1 =v cc2 =av cc ? 0.3 to 6.5 v av cc analog supply voltage v cc1 =v cc2 =av cc ? 0.3 to 6.5 v v i input voltage reset , cnvss, byte, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, vref, xin ? 0.3 to v cc +0.3 v p7_0, p7_1 ? 0.3 to 6.5 v v o output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, xout ? 0.3 to v cc +0.3 v p7_0, p7_1 ? 0.3 to 6.5 v p d power dissipation ? 40 c under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 19 of 34 rej03b0088-0080 notes: 1. referenced to v cc1 = v cc2 = 2.7 to 5.5v at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified. 2. the average output current is the mean value within 100ms. 3. the total i ol(peak) for ports p0, p1, p2, p8_6, p8_7, p9 and p10 must be 80ma max. the total i ol(peak) for ports p3, p4, p5, p6, p7 and p8_0 to p8_4 must be 80ma max. the total i oh(peak) for ports p0, p1, and p2 must be ? 20ma max. the total i oh(peak) for ports p3, p4 and p5 must be ? 40ma max. the total i oh(peak) for ports p6, p7, and p8_0 to p8_4 must be ? 40ma max. the total i oh(peak) for ports p8_6, p8_7 and p9 must be ? 40ma max. set average output current to 1/2 of peak . 4. relationship between main clock os cillation frequency, and supply voltage. table 5.2 recommended operating conditions (1) symbol parameter standard unit min. typ. max. v cc supply voltage (v cc1 =v cc2 ) 2.7 5.0 5.5 v av cc analog supply voltage v cc v v ss supply voltage 0v av ss analog supply voltage 0 v v ih high input voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte 0.8v cc v cc v p7_0, p7_1 0.8v cc 6.5 v v il low input voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte 00.2v cc v i oh(peak) high peak output current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 ? 10.0 ma i oh(avg) high average output current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 ? 5.0 ma i ol(peak) low peak output current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 10.0 ma i ol(avg) low average output current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 5.0 ma f(xin) main clock input oscillation frequency (4) v cc =4.2v to 5.5v 016mhz v cc =2.7v to 4.2v 04v cc ? 0.8 mhz f(xcin) sub-clock oscillation frequency 32.768 50 khz f(bclk) cpu operation clock 0 16 mhz main clock input oscillation frequency 16.0 10.0 0.0 2.7 4.2 5.5 operating maximum frequency [mhz] 4 v cc? 0.8mh z supply voltage [v] (main clock: no division)
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 20 of 34 rej03b0088-0080 notes: 1. referenced to v cc =av cc =v ref =3.3 to 5.5v, v ss =av ss =0v at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified. 2. ad frequency must be 10 mhz or less. 3. when sample & hold function is disabled, ad frequency must be 250 khz or more, in addition to the limitation in note 2. when sample & hold function is enabled, ad frequency must be 1mhz or more, in addition to the limitation in note 2. table 5.3 a/d conversion characteristics (1) symbol parameter measuring condition standard unit min. typ. max. ? resolution v ref =v cc 10 bits inl integral non-linearity error 10bit v ref = v cc = 5v an0 to an7 input, an0_0 to an0_7 input, anex0, anex1 input 5 lsb v ref = v cc = 3.3v an0 to an7 input, an0_0 to an0_7 input, anex0, anex1 input 7 lsb 8bit v ref =v cc =3.3v 2 lsb ? absolute accuracy 10bit v ref = v cc = 5v an0 to an7 input, an0_0 to an0_7 input, anex0, anex1 input 5 lsb v ref = v cc =3.3v an0 to an7 input, an0_0 to an0_7 input, anex0, anex1 input 7 lsb 8bit v ref =v cc =3.3v 2 lsb ? tolerance level impedance 3 k ? dnl differential non-linearity error 2 lsb ? offset error 5 lsb ? gain error 5 lsb r ladder ladder resistance v ref =v cc 10 40 k ? t conv 10-bit conversion time, sample & hold function available v ref =v cc =5v, ad=10mhz 3.3 s t conv 8-bit conversion time, sample & hold function available v ref =v cc =5v, ad=10mhz 2.8 s t samp sampling time 0.3 s v ref reference voltage 3.0 v cc v v ia analog input voltage 0 v ref v
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 21 of 34 rej03b0088-0080 figure 5.1 power supply circuit timing diagram table 5.4 power supply circuit timing characteristics symbol parameter measuring condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during powering-on v cc =2.7v to 5.5v 2 ms t d(r-s) stop release time 1500 s t d(w-s) low power dissipation mode wait mode release time 1500 s t d(p-r) v cc cpu clock cpu clock t d(r-s) (a) (b) t d(w-s) td(p-r) time for internal power supply stabilization during powering-on interrupt for (a) stop mode release or (b)wait mode release td(r-s) stop release time td(w-s) low power dissipation mode wait mode release time recommended operation voltage
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 22 of 34 rej03b0088-0080 v cc1 =v cc2 =5v notes: 1. referenced to v cc1 =v cc2 =4.2 to 5.5v, v ss = 0v at t opr = ? 20 to 85 c / ? 40 to 85 c, f(xin)=16mhz unless otherwise specified. 2. with one timer operated using fc32. 3. this indicates the memory in which the program to be executed exists. table 5.5 electrical characteristics (1) symbol parameter measuring condition standard unit min. typ. max. v oh high output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 i oh = ? 5ma v cc ? 2.0 v cc v v oh high output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 i oh = ? 200 a v cc ? 0.3 v cc v v oh high output voltage xout highpower i oh = ? 1ma v cc ? 2.0 v cc v lowpower i oh = ? 0.5ma v cc ? 2.0 v cc high output voltage xc out highpower with no load applied 2.5 v lowpower with no load applied 1.6 v ol low output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 i ol =5ma 2.0 v v ol low output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 i ol =200 a 0.45 v v ol low output voltage xout highpower i ol =1ma 2.0 v lowpower i ol =0.5ma 2.0 low output voltage xcout highpower with no load applied 0 v lowpower with no load applied 0 v t+- v t- hysteresis ta0in to ta2i n, tb0in to tb2in, int0 to int4 , nmi , adtrg , cts0 to cts2 , clk0 to clk2, ta0o ut to ta2out, ki0 to ki3 , rxd0 to rxd2, scl0 to scl2, sda0 to sda2 0.2 1.0 v v t+- v t- hysteresis reset 0.2 2.5 v v t+- v t- hysteresis xin 0.2 0.8 v i ih high input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte v i =5v 5.0 a i il low input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte v i =0v ? 5.0 a r pullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 v i =0v 30 50 170 k ? r fxin feedback resistance xin 1.5 m ? r fxcin feedback resistance xcin 15 m ? v ram ram retention voltage at stop mode 2.0 v i cc power supply current (v cc1 =v cc2 =4.2v to 5.5v) in single-chip mode, the output pins are open and other pins are v ss mask rom f(xin)=16mhz no division 10 ma f(xcin)=32khz low power dissipation mode, rom (3) 25 a f(xcin)=32khz wait mode (2) , oscillation capacity high 7.5 a f(xcin)=32khz wait mode (2) , oscillation capacity low 2.0 a stop mode topr =25 c 0.8 3.0 a
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 23 of 34 rej03b0088-0080 v cc1 =v cc2 =5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.6 external clock input (xin input) symbol parameter standard unit min. max. t c external clock input cycle time 62.5 ns t w(h) external clock input high pulse width 25 ns t w(l) external clock input low pulse width 25 ns t r external clock rise time 15 ns t f external clock fall time 15 ns
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 24 of 34 rej03b0088-0080 v cc1 =v cc2 =5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.7 timer a input (counter input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 100 ns t w(tah) taiin input high pulse width 40 ns t w(tal) taiin input low pulse width 40 ns table 5.8 timer a input (gating input in timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 400 ns t w(tah) taiin input high pulse width 200 ns t w(tal) taiin input low pulse width 200 ns table 5.9 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 200 ns t w(tah) taiin input high pulse width 100 ns t w(tal) taiin input low pulse width 100 ns table 5.10 timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min. max. t w(tah) taiin input high pulse width 100 ns t w(tal) taiin input low pulse width 100 ns table 5.11 timer a input (counter increment/ decrement input in event counter mode) symbol parameter standard unit min. max. t c(up) taiout input cycle time 2000 ns t w(uph) taiout input high pulse width 1000 ns t w(upl) taiout input low pulse width 1000 ns t su(up-tin) taiout input setup time 400 ns t h(tin-up) taiout input hold time 400 ns table 5.12 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 800 ns t su(tain-taout) taiout input setup time 200 ns t su(taout-tain) taiin input setup time 200 ns
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 25 of 34 rej03b0088-0080 v cc1 =v cc2 =5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.13 timer b input (counter input in event counter mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time (counted on one edge) 100 ns t w(tbh) tbiin input high pulse width (counted on one edge) 40 ns t w(tbl) tbiin input low pulse width (counted on one edge) 40 ns t c(tb) tbiin input cycle time (counted on both edges) 200 ns t w(tbh) tbiin input high pulse width (counted on both edges) 80 ns t w(tbl) tbiin input low pulse width (counted on both edges) 80 ns table 5.14 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 400 ns t w(tbh) tbiin input high pulse width 200 ns t w(tbl) tbiin input low pulse width 200 ns table 5.15 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 400 ns t w(tbh) tbiin input high pulse width 200 ns t w(tbl) tbiin input low pulse width 200 ns table 5.16 a/d trigger input symbol parameter standard unit min. max. t c(ad) adtrg input cycle time 1000 ns t w(adl) adtrg input low pulse width 125 ns table 5.17 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ns t w(ckh) clki input high pulse width 100 ns t w(ckl) clki input low pulse width 100 ns t d(c-q) txdi output delay time 80 ns t h(c-q) txdi hold time 0 ns t su(d-c) rxdi input setup time 70 ns t h(c-d) rxdi input hold time 90 ns table 5.18 external interrupt inti input symbol parameter standard unit min. max. t w(inh) inti input high pulse width 250 ns t w(inl) inti input low pulse width 250 ns
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 26 of 34 rej03b0088-0080 figure 5.2 timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c v cc1 =v cc2 =5v
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 27 of 34 rej03b0088-0080 figure 5.3 timing diagram (2) t su(d-c) clk i txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) int i input t d(c-q) t h(c-d) t h(c-q) v cc1 =v cc2 =5v
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 28 of 34 rej03b0088-0080 v cc1 =v cc2 =3v notes: 1. referenced to v cc1 = v cc2 = 2.7 to 3.3v, v ss = 0v at topr = ? 20 to 85 c / ? 40 to 85 c, f(xin)=10mhz no wait unless otherwise specified. 2. with one timer operated using fc32. 3. this indicates the memory in which the program to be executed exists. table 5.19 electrical characteristics (1) symbol parameter measuring condition standard unit min. typ. max. v oh high output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 i oh = ? 1ma v cc ? 0.5 v cc v v oh high output voltage xout highpower i oh = ? 0.1ma v cc ? 0.5 v cc v lowpower i oh = ? 50 av cc ? 0.5 v cc high output voltage xcout highpower with no load applied 2.5 v lowpower with no load applied 1.6 v ol low output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 i ol =1ma 0.5 v v ol low output voltage xout highpower i ol =0.1ma 0.5 v lowpower i ol =50 a0.5 low output voltage xcout highpower with no load applied 0 v lowpower with no load applied 0 v t+- v t- hysteresis ta0in to ta2in, tb0in to tb2in, int0 to int4 , nmi , adtrg , cts0 to cts2 , rxd0 to rxd2, clk0 to clk2, ta0out to ta2out, ki0 to ki3 , scl0 to scl2, sda0 to sda2 0.2 0.8 v v t+- v t- hysteresis reset 0.2 (0.7) 1.8 v v t+- v t- hysteresis xin 0.2 0.8 v i ih high input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte v i =3v 4.0 a i il low input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte v i =0v ? 4.0 a r pullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 v i =0v 50 100 500 k ? r fxin feedback resistance xin 3.0 m ? r fxcin feedback resistance xcin 25 m ? v ram ram retention voltage at stop mode 2.0 v i cc power supply current (v cc1 =v cc2 =2.7v to 3.6v) in single-chip mode, the output pins are open and other pins are v ss mask rom f(xin)=10mhz, no wait no division 8ma f(xcin)=32khz, low power dissipation mode, rom (3) 25 a f(xcin)=32khz, wait mode (2) , oscillation capacity high 7.0 a f(xcin)=32khz, wait mode (2) , oscillation capacity low 1.8 a stop mode, t opr =25 c 0.7 3.0 a
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 29 of 34 rej03b0088-0080 v cc1 =v cc2 =3v timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.20 external clock input (xin input) symbol parameter standard unit min. max. t c external clock input cycle time 100 ns t w(h) external clock input high pulse width 40 ns t w(l) external clock input low pulse width 40 ns t r external clock rise time 18 ns t f external clock fall time 18 ns
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 30 of 34 rej03b0088-0080 v cc1 =v cc2 =3v timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.21 timer a input (counter input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 150 ns t w(tah) taiin input high pulse width 60 ns t w(tal) taiin input low pulse width 60 ns table 5.22 timer a input (gating input in timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 600 ns t w(tah) taiin input high pulse width 300 ns t w(tal) taiin input low pulse width 300 ns table 5.23 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 300 ns t w(tah) taiin input high pulse width 150 ns t w(tal) taiin input low pulse width 150 ns table 5.24 timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min. max. t w(tah) taiin input high pulse width 150 ns t w(tal) taiin input low pulse width 150 ns table 5.25 timer a input (counter increment/ decrement input in event counter mode) symbol parameter standard unit min. max. t c(up) taiout input cycle time 3000 ns t w(uph) taiout input high pulse width 1500 ns t w(upl) taiout input low pulse width 1500 ns t su(up-tin) taiout input setup time 600 ns t h(tin-up) taiout input hold time 600 ns table 5.26 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 2 s t su(tain-taout) taiout input setup time 500 ns t su(taout-tain) taiin input setup time 500 ns
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 31 of 34 rej03b0088-0080 v cc1 =v cc2 =3v timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.27 timer b input (counter input in event counter mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time (counted on one edge) 150 ns t w(tbh) tbiin input high pulse width (counted on one edge) 60 ns t w(tbl) tbiin input low pulse width (counted on one edge) 60 ns t c(tb) tbiin input cycle time (counted on both edges) 300 ns t w(tbh) tbiin input high pulse width (counted on both edges) 120 ns t w(tbl) tbiin input low pulse width (counted on both edges) 120 ns table 5.28 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 600 ns t w(tbh) tbiin input high pulse width 300 ns t w(tbl) tbiin input low pulse width 300 ns table 5.29 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 600 ns t w(tbh) tbiin input high pulse width 300 ns t w(tbl) tbiin input low pulse width 300 ns table 5.30 a/d trigger input symbol parameter standard unit min. max. t c(ad) adtrg input cycle time 1500 ns t w(adl) adtrg input low pulse width 200 ns table 5.31 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ns t w(ckh) clki input high pulse width 150 ns t w(ckl) clki input low pulse width 150 ns t d(c-q) txdi output delay time 160 ns t h(c-q) txdi hold time 0 ns t su(d-c) rxdi input setup time 100 ns t h(c-d) rxdi input hold time 90 ns table 5.32 external interrupt inti input symbol parameter standard unit min. max. t w(inh) inti input high pulse width 380 ns t w(inl) inti input low pulse width 380 ns
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 32 of 34 rej03b0088-0080 figure 5.4 timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c v cc1 =v cc2 =3v
under development m16c/30p group 5. electrical characteristics preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 33 of 34 rej03b0088-0080 figure 5.5 timing diagram (2) t su(d-c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) inti input t d(c-q) t h(c-d) t h(c-q) v cc1 =v cc2 =3v
under development m16c/30p group appendix 1. package dimensions preliminary specification specifications in this manual are tentative and subject to change. rev.0.80 mar 18, 2005 page 34 of 34 rej03b0088-0080 appendix 1. package dimensions qfp100-p-1420-0.65 1.58 weight(g) jedec code eiaj package code lead material alloy 42 100p6s-a plastic 100pin 14 ? 20mm body qfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.35 i 2 1.3 m d 14.6 m e 20.6 10 0 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.65 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 0 3.05 e e e e c h e 1 30 31 81 50 80 51 h d d m d m e a f a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100 x 0.13 b x m recommended lqfp100-p-1414-0.50 weight(g) 0.63 jedec code eiaj package code lead material cu alloy 100p6q-a plastic 100pin 14 ? 14mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 0.9 m d 14.4 m e 14.4 10 0 0.1 1.0 0.7 0.5 0.3 16.2 16.0 15.8 16.2 16.0 15.8 0.5 14.1 14.0 13.9 14.1 14.0 13.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e h e 1 76 75 51 50 26 25 h d d a f y 100 lp 0.45 0.6 0.25 0.75 0.08 x a3 b x m a 1 a 2 l 1 l detail f lp a3 c m d l 2 b 2 m e e recommended mount pad recommended
c - 1 revision history m16c/30p group datasheet rev. date description page summary 0.70 aug 26, 2004 ? first edition issued 0.80 mar 18, 2005 ? development support tools -> development tools ? bclk -> cpu clock 2 table 1.1 performance outline of m16c/30p group serial interface is revised. 4 figure 1.2 type., memory size, and package is partly revised. 8 table 1.4 pin detection (2) is partly revised. 20 note 2 table 5.3 a/d conversion characteristics is partly revised. 21 symbol of table 5.4 power supply circu it timing characteristics is partly revised. 22 table 5.5 electrical characteristics is revised. 28 table 5.19 electrical ch aracteristics is revised.
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